本次仿真在Ubuntu1804环境下进行，仿真工具使用iverilog。仿真过程用到tcsh，该shell需要手动安装。
准备阶段
安装iverilog、tcsh
sudo apt-get install tcsh iverilog verilator gtkwave
相关下载
开始仿真前，需要将仓库clone到本地，并下载官方提供的RISCV交叉编译工具
wujian100仓库clone git clone https://github.com/T-head-Semi/wujian100_open.git 交叉编译工具下载
环境配置
创建工程目录
ws@laptop:~$ mkdir ~/wujian_sim
ws@laptop:~$ cd ~/wujian_sim/
ws@laptop:~/wujian_sim$ 添加wujian100仓库到该目录下
ws@laptop:~/wujian_sim$ cp -r ../wujian/wujian100_open/ ./
配置交叉编译工具 目前环境下用到的工具为工具包中的riscv64-elf-x86_64-20190731.tar.gz，需要在工程目录下新建名为riscv_toolchain的目录，并将该文件解压缩至该目录。
ws@laptop:~/wujian_sim$ mkdir riscv_toolchain
ws@laptop:~/wujian_sim$ cd riscv_toolchain/
ws@laptop:~/wujian_sim/riscv_toolchain$ tar xf ../../wujian/RISC-V\ Toolchain-V1.2.2/riscv64-elf-x86_64-20190731.tar.gzok,完成上述操作之后，就可以开始仿真了
仿真Hello Friend
根据仓库readme描述，进入tools目录
ws@laptop:~/wujian_sim/riscv_toolchain$ cd ../wujian100_open/tools/
ws@laptop:~/wujian_sim/wujian100_open/tools$切换tcsh
ws@laptop:~/wujian_sim/wujian100_open/tools$ tcsh
laptop:~/wujian_sim/wujian100_open/tools>
source环境变量
laptop:~/wujian_sim/wujian100_open/tools> source setup.csh进入work目录，仿真走起
laptop:~/wujian_sim/wujian100_open/tools> cd ../workdir/
laptop:~/wujian_sim/wujian100_open/workdir> ../tools/run_case -sim_tool iverilog ../case/timer/timer_test.c
仿真输出
laptop:~/wujian_sim/wujian100_open/workdir> ../tools/run_case -sim_tool iverilog ../case/timer/timer_test.c
Useless use of not in void context at ../tools/run_case line 204.
Step1 (Remove all things in current 'workdir') is finished!
../case/timer//timer_test.c
Step2 (Process the command line arguments) is finished!
mkdir: cannot create directory ‘../regress/regress_result’: File exists
rm -rf *.o *.pat *.elf *.obj *.hex
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o crt0.o crt0.s
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o __dtostr.o __dtostr.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o __isnan.o __isnan.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o printf.o printf.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o vprintf.o vprintf.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o sprintf.o sprintf.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o snprintf.o snprintf.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o fprintf.o fprintf.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o vfprintf.o vfprintf.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o getchar.o getchar.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o timer_test.o timer_test.c
In file included from timer_test.c:12:
vtimer.h: In function 'get_vtimer':
vtimer.h:14:14: warning: assignment to 'int *' from 'unsigned int' makes pointer from integer without a cast [-Wint-conversion]
TIMER_ADDR = 0xE0013000;
^
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o putc.o putc.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o puts.o puts.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o fputc.o fputc.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o getc.o getc.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o __isinf.o __isinf.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o putchar.o putchar.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o vsprintf.o vsprintf.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o __v_printf.o __v_printf.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o vsnprintf.o vsnprintf.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o __lltostr.o __lltostr.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -c -march=rv32emcxcki -mabi=ilp32e -De902 -Wa,--defsym=e902=1 -O3 -funroll-all-loops -fgcse-sm -finline-limit=500 -fno-schedule-insns -ffunction-sections -fdata-sections -o __ltostr.o __ltostr.c
../../riscv_toolchain/bin/riscv64-unknown-elf-gcc -Tlinker.lcf -nostartfiles -march=rv32emc -mabi=ilp32e -lc -lgcc crt0.o getchar.o vprintf.o sprintf.o snprintf.o fprintf.o __lltostr.o puts.o __isnan.o timer_test.o getc.o printf.o vsprintf.o __v_printf.o vsnprintf.o __dtostr.o vfprintf.o putc.o fputc.o __isinf.o putchar.o __ltostr.o -o timer_test.elf -lm
../../riscv_toolchain/bin/riscv64-unknown-elf-objcopy -O srec timer_test.elf timer_test.hex
rm -f *.pat
#../tools/Srec2vmem.py timer_test.hex test.pat
../tools/Srec2vmem.py -i timer_test.hex -o test.pat
../../riscv_toolchain/bin/riscv64-unknown-elf-objdump -S -Mnumeric timer_test.elf > timer_test.obj
make clean; make all CPU=e902m ENDIAN_MODE=little-endian FILE=timer_test HGPR=
Step3 (Make) is finished!
Use of uninitialized value $had_v in concatenation (.) or string at ../tools/run_case line 241.
warning: Found both default and `timescale based delays. Use
-Wtimescale to find the module(s) with no `timescale.
######time: 0, Dump start######
VCD info: dumpfile test.vcd opened for output.
******START TO LOAD PROGRAM******
Hello Friend!
timer test successfully
***************************************
* Test Pass *
***************************************
Step4 (Run simulation) is finished总结
- Ubuntu默认使用bash shell,仿真环境配置文件setup.csh需要用tcsh,so 切换的tcsh至关重要；
- 仿真过程需要使用交叉编译工具，且目录必须与仓库所在目录一致，注意交叉编译工具文件夹的命名。
文章来源：芯片开放社区
文章链接：https://occ.t-head.cn/community/post/detail?spm=a2cl5.14300636.0.0.1b87180flWxVN5&id=650362409306816512
