05 存储器
VL53 单端口RAM
`timescale 1ns/1ns module RAM_1port( input clk , input rst , input enb , input [ 6:0] addr , input [ 3:0] w_data , output wire [ 3:0] r_data ); //*************code***********// reg [3:0] ram_reg [127:0]; //存储宽度为4位，深度为128 reg [ 3:0] r_data_ache ; integer i; always @(posedge clk or negedge rst) begin if(!rst) begin for (i =0 ; i < 128; i = i + 1) begin ram_reg[i] <= 4'b0; end end else begin if(enb) begin ram_reg[addr] <= w_data; end else begin ram_reg[addr] <= ram_reg[addr]; end end end assign r_data = enb ? 4'd0 : ram_reg[addr]; //*************code***********// endmodule
VL54 RAM的简单实现
`timescale 1ns/1ns module ram_mod( input clk , input rst_n , input write_en , input [ 7:0] write_addr , input [ 3:0] write_data , input read_en , input [ 7:0] read_addr , output reg [ 3:0] read_data ); reg [3:0] ram_reg [127:0]; integer i; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin for (i = 0;i<128 ; i = i + 1) begin ram_reg[i] <= 4'b0; end read_data <= 4'd0; end else begin if(write_en) begin ram_reg[write_addr] <= write_data; end if(read_en) begin read_data <= ram_reg[read_addr]; end end end endmodule
06 综合
VL55 Johnson Counter
`timescale 1ns/1ns module JC_counter( input clk , input rst_n , output reg [ 3:0] Q ); reg [ 2:0] data_cnt ; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin data_cnt <= 3'b0; end else begin data_cnt <= data_cnt + 1'd1; end end always @(posedge clk or negedge rst_n) begin if (!rst_n) begin Q <= 4'd0; end else begin if (data_cnt <= 4'd3) begin Q <= (Q>>1) | 1000; end else begin Q <= (Q>>1); end end end endmodule
VL56 流水线乘法器
`timescale 1ns/1ns module multi_pipe#( parameter size = 4 )( input clk , input rst_n , input [size-1:0] mul_a , input [size-1:0] mul_b , output reg [size*2-1:0] mul_out ); /********************************************************************/ reg [7:0] addr01; reg [7:0] addr23; wire [7:0] temp0 ; wire [7:0] temp1 ; wire [7:0] temp2 ; wire [7:0] temp3 ; assign temp0 = mul_b[0]? {4'b0, mul_a} : 'd0; assign temp1 = mul_b[1]? {3'b0, mul_a, 1'b0} : 'd0; assign temp2 = mul_b[2]? {2'b0, mul_a, 2'b0} : 'd0; assign temp3 = mul_b[3]? {1'b0, mul_a, 3'b0} : 'd0; always @(posedge clk or negedge rst_n) begin if(~rst_n) begin addr01 <= 'd0; addr23 <= 'd0; mul_out <= 'd0; end else begin addr01 <= temp0 + temp1; addr23 <= temp2 + temp3; mul_out <= addr01 + addr23; end end endmodule
VL57 交通灯
`timescale 1ns/1ns module triffic_light ( input rst_n, //异位复位信号，低电平有效 input clk, //时钟信号 input pass_request, output wire[7:0]clock, output reg red, output reg yellow, output reg green ); endmodule
VL58 游戏机计费程序
`timescale 1ns/1ns module game_count ( input rst_n, //异位复位信号，低电平有效 input clk, //时钟信号 input [9:0]money, input set, input boost, output reg[9:0]remain, output reg yellow, output reg red ); always @(posedge clk or negedge rst_n) begin if (!rst_n) begin remain <= 'd0; end else begin if(set) begin remain <= money + remain; end else if (boost) begin if (remain < 'd2) begin remain <= 'd0; end else begin remain <= remain - 'd2; end end else if (!boost) begin if (remain < 'd1) begin remain <= 'd0; end else begin remain <= remain - 'd1; end end else begin remain <= remain; end end end always @(posedge clk or negedge rst_n) begin if (!rst_n) begin red <= 1'd0; end else begin if(remain < 'd1) begin red <= 1'd1; end else begin red <= 1'd0; end end end always @(posedge clk or negedge rst_n) begin if (!rst_n) begin yellow <= 1'd0; end else begin if(yellow < 'd10 && yellow > 'd0) begin yellow <= 1'd1; end else begin yellow <= 1'd0; end end end endmodule
