VL47 格雷码计数器
`timescale 1ns/1ns module gray_counter( input clk , input rst_n , output reg [ 3:0] gray_out ); reg [ 3:0] binary_cnt ; reg flag ; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin flag <= 1'd0; end else begin flag <= ~flag; end end always @(posedge clk or negedge rst_n) begin if (!rst_n) begin binary_cnt <= 1'd0; end else begin if (flag == 1'd1) begin binary_cnt <= binary_cnt + 1'd1; end else begin binary_cnt <= binary_cnt; end end end always @(*) begin gray_out <= binary_cnt ^ (binary_cnt >> 1); end endmodule
VL48 多bit MUX同步器
`timescale 1ns/1ns module mux( input clk_a , input clk_b , input arstn , input brstn , input [3:0] data_in , input data_en , output reg [3:0] dataout ); endmodule
VL49 脉冲同步电路
`timescale 1ns/1ns module pulse_detect( input clk_fast , input clk_slow , input rst_n , input data_in , output dataout ); reg src_state ; reg src_state_d0 ; reg src_state_d1 ; reg src_state_d2 ; //原时钟域下脉冲信号转变为电平信号 always @(posedge clk_fast or negedge rst_n) begin if(!rst_n) src_state <= 1'b0; else src_state <= data_in ^ src_state; //通过异或门做处理 end always @(posedge clk_slow or negedge rst_n) begin if (!rst_n) begin src_state_d0 <= 1'b0; src_state_d1 <= 1'b0; src_state_d2 <= 1'b0; end else begin src_state_d0 <= src_state; src_state_d1 <= src_state_d0; src_state_d2 <= src_state_d1; end end //边沿检测产生新的脉冲 assign dataout = src_state_d1 ^ src_state_d2; endmodule
04 计数器
VL50 简易秒表
`timescale 1ns/1ns module count_module( input clk , input rst_n , output reg [ 5:0] second , output reg [ 5:0] minute ); always @(posedge clk or negedge rst_n) begin if(!rst_n) begin second <= 'd0; //minute <= 'd0; end else begin if(second == 6'd60) begin second <= 1'd1; end else begin second <= second + 1'd1; end end end always @(posedge clk or negedge rst_n) begin if (!rst_n) begin minute <= 1'd0; end else begin if (second == 6'd60) begin minute <= minute + 1'd1; end if (minute == 6'd60) begin minute <= 1'd0; end end end endmodule
VL51 可置位计数器
`timescale 1ns/1ns module count_module( input clk , input rst_n , input set , input [ 3:0] set_num , output reg [ 3:0] number , output reg zero ); reg [ 3:0] data_cnt ; //定义计数器 always @(posedge clk or negedge rst_n) begin if (!rst_n) begin data_cnt <= 'd0; end else begin if(set == 1'd1) begin data_cnt <= set_num; end data_cnt <= data_cnt + 1'd1; end end // always @(posedge clk or negedge rst_n) begin if (!rst_n) begin zero <= 1'd0; end else begin if (data_cnt == 1'd0) begin zero <= 1'd1; end else begin zero <= 1'd0; end end end always @(posedge clk or negedge rst_n) begin if (!rst_n) begin number <=4'd0; end else begin number <= data_cnt; end end endmodule
VL52 加减计数器
`timescale 1ns/1ns module count_module( input clk , input rst_n , input mode , output reg [ 3:0] number , output reg zero ); reg [ 3:0] data_cnt ; always @(posedge clk or negedge rst_n) begin if (!rst_n) begin data_cnt <= 4'd0; end else begin if(mode == 1'd1) begin if(data_cnt == 4'd9) begin data_cnt <= 1'd0; end else begin data_cnt <= data_cnt + 1'd1; end end else if(mode == 1'd0) begin if (data_cnt == 4'd0) begin data_cnt <= 4'd9; end else begin data_cnt <= data_cnt - 1'd1; end end end end always @(posedge clk or negedge rst_n) begin if (!rst_n) begin number <= 4'd0; end else begin number <= data_cnt; end end always @(posedge clk or negedge rst_n) begin if(!rst_n) begin zero <= 1'd0; end else begin if(data_cnt == 1'd0) begin zero <= 1'd1; end else begin zero <= 1'd0; end end end endmodule
