1. Verilog快速入门
1. 基础语法
VL1 四选一多路器
`timescale 1ns/1ns module mux4_1( input [ 1:0] d1,d2,d3,d0 , input [ 1:0] sel , output [ 1:0] mux_out ); //*************code***********// /* reg [ 1:0] state ; always @(*) begin case (sel) 2'b00:state = d3; 2'b01:state = d2; 2'b11:state = d0; 2'b10:state = d1; default:state = d3; endcase end assign mux_out = state; */ assign mux_out = sel[1]==1?(sel[0]==1?d0:d1):(sel[0]==1?d2:d3); //*************code***********// endmodule
VL2 异步复位的串联T触发器
`timescale 1ns/1ns module Tff_2 ( input wire data, clk, rst , output reg q ); reg data1 ; always @(posedge clk or negedge rst) begin if(!rst) begin data1 <= 1'b0; end else begin if (data) begin data1 <= !data1; end else begin data1 <= data1; end end end always @(posedge clk or negedge rst) begin if(!rst) begin q <= 1'b0; end else begin if (data1) begin q <= !q; end else begin q <= q; end end end endmodule
LV3 奇偶校验
`timescale 1ns/1ns module odd_sel( input [ 31:0] bus , input sel , output check ); //*************code***********// reg state; always @(*) begin case (sel) 1'b1: if(^bus == 1) begin state = 1; end else begin state = 0; end 1'b0: if (^bus == 0) begin state = 1; end else begin state = 0; end default: state = 0; endcase end assign check = state; endmodule
VL4 移位运算与乘法
`timescale 1ns/1ns module multi_sel( input [7:0]d , input clk, input rst, output reg input_grant, output reg [10:0]out ); reg [1:0] state; reg [7:0] din; always @(posedge clk or negedge rst) begin if(!rst)begin out <= 11'b0; state <= 2'b00; input_grant <= 0; din <= 0; end else begin case (state) 2'b00:begin input_grant <= 1; din <= d; out <= d; //out <= (din<<2) - din; state <= 2'b01; end 2'b01: begin out <= (din<<2) - din; input_grant <= 0; state <= 2'b10; end 2'b10:begin out <= (din<<3) - din; input_grant <= 0; state <= 2'b11; end 2'b11: begin out <= (din<<3); input_grant <= 0; state <= 2'b00; end default:begin state <= 2'b00; input_grant <= 0; end endcase end end endmodule
LV5 位拆分与运算
`timescale 1ns/1ns module data_cal( input clk , input rst , input [ 15:0] d , input [ 1:0] sel , output [ 4:0] out , output validout ); reg [ 4:0] out_map ; reg [ 15:0] d_luck ; reg validout_tmp ; always @(posedge clk or negedge rst) begin if(!rst)begin out_map <= 5'd0; validout_tmp<=1'b0; end else begin case (sel) 2'd0: begin d_luck <= d; validout_tmp<=1'b0; out_map <= 5'd0; end 2'd1: begin out_map <= d_luck[3:0] + d_luck[7:4]; validout_tmp<=1'b1; end 2'd2: begin out_map <= d_luck[3:0] + d_luck[11:8]; validout_tmp<=1'b1; end 2'd3: begin out_map <= d_luck[3:0] + d_luck[15:12]; validout_tmp<=1'b1; end default:begin out_map <= 5'd0; validout_tmp<=1'b0; end endcase end end assign out = out_map; assign validout = validout_tmp; endmodule
VL6 多功能数据处理器
`timescale 1ns/1ns module data_select( input clk , input rst_n , input signed [ 7:0] a , input signed [ 7:0] b , input [ 1:0] select , output reg signed [ 8:0] c ); always @(posedge clk or negedge rst_n) if(!rst_n) c <= 9'd0; else case(select) 2'b00: c <= a; 2'b01: c <= b; 2'b10: c <= a+b; 2'b11: c <= a-b; default: c <= 9'd0; endcase endmodule
VL7 求两个数的差值
`timescale 1ns/1ns module data_minus( input clk , input rst_n , input [ 7:0] a , input [ 7:0] b , output reg [ 8:0] c ); always @(posedge clk or negedge rst_n) begin if(!rst_n)begin c <= 9'b0; end else begin if (a>b) begin c <= a - b; end else if(a <= b) begin c <= b - a; end end end endmodule
